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    • 专利摘要:
    The present invention relates to a coated flexible component comprising a flexible substrate (100) and at least one layer structure arranged on the substrate (100) directly or via one or more intermediate layers, comprising a metallic layer (120; 170a; 170b) with one Side to the metallic layer directly adjacent semiconducting or electrically insulating layer (100; 110; 140; 150; 180) and to the other side to the metallic layer immediately adjacent semiconducting or electrically insulating layer (100; 110; 140; 150; 180) having. The metallic layer (120; 170a; 170b) is formed of a single layer of MoX, or of a two-layer system of MoX in combination with a Cu-based layer or of MoX in combination with an Al-based layer, or of a three-layer system of two MoX layers with intervening Cu-based layer or two MoX layers with intervening Al-based layer, wherein X is one or more elements from the group of Cu, Ag, Au.
    公开号:AT15574U2
    申请号:TGM104/2017U
    申请日:2017-05-11
    公开日:2018-03-15
    发明作者:Köstenbauer Harald；Winkler Jörg
    申请人:Plansee Se；
    IPC主号:
    专利说明:

    description
    FLEXIBLE COMPONENT WITH LAYER STRUCTURE WITH METAL LAYER The invention relates to the use of an additive for maintaining an electrical conductivity of a Mo-based layer within the layer plane with the features of the preamble of claim 1, a coated flexible component with the features of the preamble of the claim 2 and a method for producing a coated flexible component with the features of the preamble of claim 20.
    Technical progress in the field of flexible, flexible components is closely linked to progress in the field of thin-film materials. In particular, this progress enables further developments in the field of electronics, in particular thin-film components, such as thin-film transistors (Thin Film Transistor / TFT), as part of a structure for active control (active matrix or "active matrix" in English) of electronic screens (Displays), e.g. Liquid crystal displays (TFTLCDs), AM-OLEDs (active matrix organic light emitting diodes; organic light-emitting diodes with active matrix control), or Micro-LED (light emitting diodes) displays. The active matrix structure can also be used in other applications, e.g. Sensor arrays for X-rays are used. In these applications, electrical conductor tracks are arranged in a matrix-like manner as rows (“gate lines”; “rows”) and columns (“signal lines”; “column lines”; “data lines”). The conductor tracks provide an electrically conductive path for the transmission of electrical signals, electrical current, or electrical voltage from one point to another.
    Each active matrix row or column consists of a long, narrow conductor track (z. B. with a length of a few centimeters to almost 2 meters, a width of a few microns to a few tens of microns and a total layer thickness of a few ten to a few hundred nanometers), each of which has one or more extensions in the area of the thin-film transistors, which form the gate (“control electrode”) or source / drain electrodes (“inflow and“ outflow electrode) ”of the TFT. The conductor tracks connect the gate or source / drain electrodes of the TFT to the edge area of the substrate, where either contact areas ("contact pads") for external contacting, or the gate and data driver structures (row and column drivers) for controlling the display are arranged.
    With the help of the active matrix control, the brightness of each individual pixel (pixel) can be individually controlled via one (e.g. TFT-LCD) or more (e.g. AM-OLED display) TFTs; It is crucial that the voltage drop along the long gate and signal conductor tracks is as small as possible, since otherwise length-dependent, undesired differences in brightness would result in the pixels. (The human eye reacts very sensitively to differences in brightness.) In the case of active matrix structures which are arranged on flexible, flexible, or rotatable substrates, the long row and column conductor tracks in particular are subject to high deformation or bending or Subject to torsional stress, this stress being much lower for the gate and source / drain electrodes in the TFT structure due to the much smaller spatial extent (typically a rectangular area with edge lengths of a few micrometers to a few tens of micrometers). Due to this stress, the electrical resistance can quickly increase by several orders of magnitude, particularly in the case of brittle conductor track materials. As a result, the TFTs arranged along the conductor track are no longer supplied with a defined voltage evenly and length-dependent differences in brightness can occur in a display application. In extreme cases, the conductor track loses its electrical conductivity completely and there is a total loss of pixels.
    Particularly in displays for mobile applications, e.g. B. Mobile phones, tablet PCs, PDAs (Personal Digital Assistants) are on the display substrate next to the actual / 31
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    Additional peripheral electrical circuits integrated to display the image content. This can e.g. B. circuits for controlling the gate electrodes (gate driver), circuits for controlling the source / drain electrodes (data driver), DC-DC converter, digital-analog converter, timing controller, or buffer and interface circuits. Such a combination of display and its control unit is referred to as a system-on-panel (SOP) (system on display panel) or - if the substrate consists of glass - as a system-on-glass (SOG) (system on glass). It is advantageous to arrange the peripheral electrical circuits for driving the display directly on the substrate, instead of designing them as external integrated circuits (ICs) with a separate housing; Significant advantages are lower manufacturing costs, lower power consumption, less space and higher reliability. System-on-panel displays are often implemented using low-temperature poly-silicone (LTPS) technology, but are also possible with other semiconductors such as amorphous silicon or metal oxides.
    Parts of the peripheral circuits arranged on the substrate are connected via electrical conductor tracks, the gate lines and signal lines to the TFTs of the individual pixels, the length, depending on the display size, being from a few mm to 200 cm. The change in resistance of the conductor tracks under deformation, bending or torsion loading should be as minimal as possible in order to prevent failure of individual pixels or entire lines or columns of the display or to avoid undesirable differences in the brightness or color ("Mura") of the display to prevent.
    Flexible touch sensors (e.g. resistive or capacitive sensors) also use x and y electrodes arranged in a matrix, but generally without active TFT structures. For larger sensors from a few centimeters to meters in size, very long, narrow conductor track structures are also used, e.g. B. with a length of 10 - 100 cm and a width of 5-50 gm. Also in this application, the change in resistance (increase) of the conductor tracks under deformation, bending or torsion loading should be as minimal as possible, otherwise there would be a failure of the Sensor (e.g. by reducing the signal-to-noise ratio).
    In WO 2016/032175 (Figure 7) to reduce the mechanical stresses in conductor tracks that are exposed to bending stress, non-linear, z. B. sinusoidal, corrugated, rectangular wave, meandering, or sawtooth waveform conductor structures proposed. In order to prevent the crack from spreading, branching and reuniting conductor track structures (FIG. 8c in the above-mentioned document) are also proposed. However, all of these structures require more space than a simple rectilinear conductor track and the electrical current as a whole has to travel a longer distance between two points, which can lead to an additional voltage drop or a reduction in the signal-to-noise ratio.
    Furthermore, advances in the development of new integration processes also enable the combination of electronics with flexible substrates and, subsequently, the production of flexible electronic components. The generic state of the art is formed by AT 15 048 U1. For further information on the prior art, reference is made to this document.
    The object of the invention is to preserve the electrical conductivity of a metallic layer which is applied to a flexible substrate which is subjected to a single or repeated bending, tensile and / or torsional stress. In particular, the object of the present invention is to provide electrical conductor tracks (metallic layers) on a flexible substrate, wherein the electrical resistance of the conductor tracks along the conductor track, i. H. within the layer plane, as little as possible, in particular by less than 10%, with a deformation, bending or torsion load.
    This object is achieved by a use according to claim 1, a coated flexible component according to claim 2 and a method for producing a coated flexible component with the features of claim 20. Advantageous embodiments of the invention are defined in the dependent claims.
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    Patent Office The invention ensures that the electrical conductivity of the Mo-based (molybdenum-based) layer or the metallic layer within a single or repeated bending and / or tensile and / or torsional loading of the flexible component the layer level is preserved. This is done by increasing ductility.
    On a flexible substrate, several metallic layers, as defined in claim 2, can also be provided, with the restriction then applying to each metallic layer that a semiconducting or electrically insulating layer is directly adjacent on both sides and the metallic layer is itself designed according to claim 2 as a single layer, two-layer system or three-layer system.
    A Mo-based layer or the MoX layer contains at least 50% by weight of Mo, in particular at least 60% by weight of Mo.
    The MoX layer can be made up of several MoX with different X containing MoX partial layers.
    Apart from the preservation of the electrical conductivity, the increase in ductility causes an increase in the mechanical damage tolerance. For example, the risk of delamination in the multilayer composite decreases.
    Of course, apart from the additive X, the Mo-based layer (MoX layer) does not have to be pure Mo, but impurities may also be present, in particular impurities which arise from the process atmosphere of a PVD (physical vapor deposition) ; physical vapor phase deposition) process, in particular a sputtering process (sputtering), (e.g. Ar, Ο, N, C). The metallic impurities should be <0.5 at%.
    Of the elements mentioned Cu, Ag, Au, Cu is particularly preferred. Here, a lower concentration in at% is sufficient to achieve the desired effect. It is also cheaper than Ag and Au.
    According to the invention, the layer structure has a metallic layer with a semiconducting or electrically insulating layer directly adjacent to the metallic layer on one side and a semiconducting or electrically insulating layer directly adjacent to the metallic layer on the other side, these properties at least in a certain area of a coated, flexible component (but not necessarily in all areas of a flexible component, in particular a flexible electronic component). Further possible adjacent layers are described in more detail below. “Electrically insulating” is understood to mean that the electrical resistance is greater than 1 megohm.
    Flexibility and “flexible” is understood here to mean the property of absorbing or withstanding a bending stress without adverse effects on the properties relevant to the use of the component. Sufficiently flexible components also have significantly improved toughness.
    Significantly improved toughness in the sense of the present invention is to be understood that the component or of course the layer or layers contained have increased resistance to crack formation and crack growth, that is to say cracks do not form or form up to a certain elongation only form at higher elongation or have a modified crack pattern.
    In order to describe the toughness and subsequently the flexibility, the critical elongation is used in the context of the present invention. The critical strain is defined as the strain c k at which the electrical resistance R of the layer or layers on the flexible substrate has increased by 10% compared to the initial state (R / R o = 1.1). In the case of components with sufficient flexibility, the critical elongation c k is significantly increased, so the conductivity of the layer or layers is retained significantly longer. In the context of the present invention, a substrate is closed under a flexible substrate
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    Understand the patent office that, when a bending load is applied, causes an elongation ε in a layer or layers (coating) deposited thereon. If the layer or layers is or are much thinner than the substrate, the elongation is approximately described by e = ds / 2R (ds is the thickness of the substrate and R is the bending radius). If the layer or the layers are very thin compared to the substrate, the elongation in the layer or in the layers can be roughly equated to a pure tensile or compressive stress. For example, a flexible substrate based on one or more polymeric materials, for example polyimide, polycarbonate, polyethylene terephthalate, polyethylene naphthalate, polyether sulfone, polyarylate or polycyclic olefin, can be constructed. Most flexible substrates based on one or more polymeric materials have an elastic modulus of less than or equal to 8 GPa. Thin glass (glass with a thickness of less than 1 mm), metal foils, for example sheet steel with a thickness of less than 1 mm, aluminum, copper or titanium foils with a thickness of less than 1 mm, or mineral materials such as mica, are also suitable flexible substrates for a flexible component according to the invention.
    A flexible substrate suitable for the invention can in turn consist of one or more layers or one or more materials. Likewise, such a substrate can be completely or only partially coated beforehand with one or more layers of other materials.
    [0026] This component is preferably a coated, flexible electronic component. In contrast to a coated flexible component such as packaging films with metallic vapor barrier layers or optical layers, a coated flexible electronic component has at least one layer that conducts the electrical current. This is for example in flexible circuits, flexible displays, flexible sensor elements, flexible thin film capacitors, flexible thin film batteries or simple electrically conductive foils, e.g. B. flexible circuit boards (printed circuit boards) the case. Examples of such flexible electronic components that can be designed according to the present invention are described in the introductory part.
    The metallic layer of a coated flexible component according to the invention preferably has a thickness of less than 1 pm. The metallic layer preferably has a minimum thickness of 5 nm, more preferably a thickness of at least 10 nm. A thickness of 5 to 300 nm is also preferred, even more preferably 5 to 100 nm. Such layer thicknesses are particularly advantageous if the metallic Location is used as an adhesion promoter layer or diffusion barrier layer. Alternatively, a thickness range of 150 to 400 nm is preferred. A layer thickness of 150 to 400 nm is particularly well suited for use of a coated flexible component according to the invention in a display, for example as a gate electrode layer.
    One or more metallic layer (s), as specified in claim 2 and possibly in one of the further developments, can be part of a thin film transistor (TFT).
    In one embodiment of the component according to the invention it can be provided that in at least one MoX layer X the element is Cu and this MoCu layer contains more than 0.5 at% and less than 50 at% Cu, preferably more than 1 at% and less than 20 at% Cu. It is particularly preferred that all MoX layers of the metallic layer are made of MoCu.
    In one embodiment of the component according to the invention it can be provided that the element is Ag in at least one MoX layer X and this MoAg layer contains more than 10 at% and less than 50 at% Ag, preferably more than 20 at% and contains less than 50 at% Ag. It is particularly preferably provided that all MoX layers of the metallic layer are made of MoAg.
    [0031] In one embodiment of the component according to the invention, it can be provided that
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    Patent office that in at least one MoX layer X the element is Au and this metallic MoAu layer contains more than 5 at% and less than 20 at% Au. It is particularly preferred that all MoX layers of the metallic layer are made of MoAu.
    In one embodiment of the component according to the invention it can be provided that the individual MoX layer has a sheet resistance p of less than 200 pOhmcm, preferably less than 100 pOhmcm, particularly preferably less than 50 pOhmcm.
    In one embodiment of the component according to the invention it can be provided that at least one of the semiconducting or electrically insulating layers directly adjacent to the metallic layer is formed as layers. It can be provided that both immediately adjacent semiconducting or electrically insulating layers are formed as layers.
    In one embodiment of the component according to the invention it can be provided that the metallic layer has a sheet resistance p of less than 50 pOhmcm, preferably less than 10 pOhmcm, particularly preferably less than 3.5 pOhmcm.
    In a method according to the invention, at least one MoX layer is deposited which contains more than 0.5 at% and less than 50 at% X, where X is one or more elements from the group of Cu, Ag, Au. The MoX layer can form a metallic layer as defined in claim 2 or be part of the same.
    [0036] The at least one MoX layer or the metallic layer can be deposited using various deposition methods. For example, such a coating can be realized by physical or chemical vapor deposition.
    However, it is advantageous if the deposition of the at least one MoX layer or the metallic layer is carried out by means of a PVD method, in particular a sputtering method. PVD processes (physical vapor deposition) are known thin-film coating technologies in which particles of the coating material are converted into the vapor phase and then deposited on the substrate. A particularly homogeneous coating can be deposited by means of a PVD process, the properties of which are the same and isotropic over the coated surface. Other advantages of this process are the low substrate temperatures that can be achieved with it. This enables, for example, the coating of polymers. Furthermore, PVD layers are characterized by very good adhesion to the substrate.
    It is particularly preferred if the MoX layer or the metallic layer is deposited using a sputtering process (also: cathode sputtering process).
    A sputtering process can be used relatively easily for the homogeneous coating of large areas and is therefore an inexpensive method for mass production.
    It is very particularly preferred if the method according to the invention further contains the following step:
    - Providing a Mo-based target that contains between 0.5 at% and less than 50 at% X.
    The provision of a Mo-based target, which contains between 0.5 at% and less than 50 at% X, takes place before the deposition of at least one MoX layer or at least one metallic layer. The MoX layer or the metallic layer is thus deposited from the target provided.
    [0043] Target is to be understood as a coating source for a coating system. In a preferred method, the target used is a sputtering target for a sputtering method.
    [0044] The chemical composition of the coating is determined via the chemical composition
    AT15 574U2 2018-03-15 Austrian
    Patent office determination of the target used. However, slightly different sputtering behavior (sputtering yields) of the elements contained in the target can lead to deviations in the coating composition from the target composition.
    For example, the Cu content in the deposited coating can be slightly increased by preferred sputtering of Cu from a MoCu target. For example, in order to produce coatings that are to contain more than 10 at% Cu, a corresponding target can also contain less than 10 at% Cu.
    [0046] As an alternative to using a single target, the metallic layer can also be deposited from individual targets via co-deposition, preferably co-sputtering. In this case, the chemical composition of the coating can also be controlled via the choice of the different targets.
    The production of sputtering targets, which are suitable for the deposition of metallic layers, can be done, for example, by powder metallurgy.
    Possible powder metallurgical routes for the production of sputtering targets are based on hot pressing technologies such as hot pressing (HP) or spark plasma sintering (SPS). In both cases, a powder mixture is filled into a mold of a press, heated in the mold and sintered / compacted to form a tight component at high pressure and temperature. This creates a homogeneous microstructure with uniform grains, which has no preferred orientation (texture).
    A similar powder metallurgical route for the production of sputtering targets is hot isostatic pressing (HIP). The material to be compacted is filled into a deformable, tight container (usually a steel can). This can be powder, powder mixtures or green bodies (powder pressed in the form). The material in this container is sintered / compressed in the container in a pressurized boiler at high temperatures and pressures under protective gas (e.g. Ar). The gas pressure acts from all sides, which is why this process is called isostatic pressing. Typical process parameters are e.g. B. 1100 ° C and 100 MPa with a holding time of 3 h. This creates a homogeneous microstructure with uniform grains, which has no preferred orientation (texture).
    A further possibility for producing sputter targets via a powder metallurgical route is sintering and subsequent forming. A powder compact is sintered at high temperature under hydrogen or vacuum.
    After the sintering, a forming step, such as rolling or forging, is carried out in order to obtain a high relative density of> 99%. This creates a microstructure with elongated grains, which has a preferred orientation (texture). In the case of an optional subsequent stress relieving annealing or recrystallization annealing, a homogeneous microstructure with uniform grains is obtained, but still has a preferred orientation (texture).
    Another possibility for producing sputter targets via a powder metallurgical route is the application of a powder or a powder mixture to a corresponding support structure, for example a plate or a tube, by means of a thermal spraying process, for example cold gas spraying or vacuum plasma spraying (VPS).
    The invention is described in more detail below with the aid of exemplary embodiments and with reference to the figures.
    [0054] The figures show:
    Figure 1 is a schematic structure of the uniaxial tensile test used with electrical resistance measurement to determine the critical elongation at break c k
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    Patent Office [0056] Figure 2 [0057] Figure 3 [0058] Figure 4 [0059] Figure 5 [0060] Figure 6 [0061] Figure 7 [0062] Figure 8 [0063] Figure 9 [0064] Figure 10 [0065] Figure 11 Figure 12
    R / R o curves for Mo and MoCu alloys depending on the Cu content in the layer
    Electron microscope images of the crack pattern of a Mo layer and various MoCu layers after a maximum elongation of 15%
    R / R o curves for Mo and MoAg alloys depending on the Ag content in the layer
    Electron microscopic images of the crack image of a Mo layer and various MoAg layers after a maximum elongation of 15% layer structure of a bottom gate thin-film transistor in cross section Schematic block diagram of a system-on-panel display (from above)
    Detail of a system-on-panel display, which shows the conductor structures between driver circuits and TFT display area from above
    Section of the TFT display structure (from above; top view), which shows how the gate and source / drain electrodes of the TFT are connected to the gate and data lines.
    Cross-sectional layer structure of a top gate LTPS-TFT
    X-ray diffractograms of sputtered 500 nm thick MoCu thin layers on a silicon wafer
    X-ray diffractograms of sputtered 500 nm thick MoAg thin layers on a silicon wafer
    EXAMPLE 1:
    In the course of several test series, different metallic layers based on Mo were deposited on polyimide substrates. Layers with different chemical compositions were manufactured.
    The compositions of the metallic Mo-based layers are summarized in Table 1.
    Table 1: Chemical composition of the sputtered MoCu layers
    Mo [at%] Cu [at%] Layer 1 93 7 Layer 2 82 18 Layer 3 66 34 Layer 4 48 52
    Pure Mo, in the form of a molybdenum layer with a thickness of 50 nm, was used as the reference material for the molybdenum-based alloys.
    All layers were deposited on a 50 pm thick film made of polyimide (PI, eg "Kapton®") at room temperature. The process parameters were kept constant in order to rule out the influence of different process conditions on the results as much as possible. The layer thickness was kept constant at 50nm to avoid the influence of geometric effects on the results.
    The substrate surface was completely coated, there were no smaller structures by z. B. etching process.
    A uniaxial tensile test was carried out on the layer samples on the polyimide substrates
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    Patent office of an MTS Tyron 250® universal testing machine carried out. The experimental setup is shown schematically in FIG. 1. The substrates were elastically deformed up to a maximum elongation 8 of 15%. During the tensile test, the electrical resistance of the layers R was continuously recorded using the four point method. The electrical resistance at the start of the measurement is referred to as R o . The sample length (free length between the clamps) in the initial state was 20mm and the width 5mm.
    The measurement set-up is shown schematically in FIG. 1. Lconst denotes the fixed clamping length within which no stretching takes place. The critical strain was defined as the strain c k at which the electrical resistance of the layers R on the flexible substrate increased by 10% compared to the initial state, that is to say R / R o = 1.1.
    The critical strains c k determined by means of this tensile test are listed in Table 2.
    Table 2: Critical strain c k of the examined Mo and MoCu layers, as well as the difference to the reference sample made of pure Mo. Furthermore, the sheet resistance of a 500 nm thick layer on a non-conductive borosilicate glass (Corning Eagle XG®) is given.
    material critical elongation c k Δε κ Sheet resistance p (pOhmcm) Mo 1.10% reference 22 MoCu 7at% 1.76% 0.66 77 MoCu 18at% 2.09% 0.99 119 MoCu 34at% 2.13% 1.03 132 MoCu 52at.% 3.23% 2.13 97
    Figure 2 shows the increase in electrical resistance compared to the output resistance (R / R o ) compared to the applied strain ε. The curve "Theory" denotes the increase in electrical resistance, which only results from the change in shape of the sample. As can be seen in the curves measured on the reference materials, the electrical resistance increases very strongly with increasing elongation.
    After the tensile test described above, the tested layers were examined in a light microscope and scanning electron microscope. The shape of the cracks and the mean distance between the cracks that occurred in the layers were assessed.
    In a layer based on a brittle material, such as pure Mo, a crack pattern typically occurs when the sample fails under tensile stress, which is typical of brittle material behavior. This is characterized by a network of straight, parallel cracks that form approximately at right angles to the direction of loading. Such a crack pattern can be seen, for example, in FIGS. 3 (Mo, left). These straight cracks usually run from side to side across the entire width of the sample and through the entire thickness of the layer. Such cracks are also called Through Thickness Cracks (TTC). TTCs considerably reduce the electrical conductivity of the layer, since in the worst case there is no longer a continuous conductive connection in the layer.
    The critical strains in Table 2 from the failure criterion R / Ro = 1.1 show that with increasing Cu content in the layer, the toughness of the layer is increased. It is believed that this increase in toughness is caused by an easier dislocation movement in the material. This subsequently leads to an increase in the critical elongation and to a reduced occurrence of TTCs.
    As an example, FIG. 2 shows the resistance curve R / R o of the MoCu 7at.% Samples. The appearance of the cracks still corresponds to the TTCs, but the critical elongation c k is already significantly increased.
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    Patent Office Another effect that can be observed in addition to increasing the critical elongation c k is that the appearance of the cracks changes from a brittle to a tough material behavior. Cracks that are typical for tough material behavior can be recognized by the fact that the cracks are no longer straight, but rather have a zigzag course. Redirecting the cracks at the crack tips is a possible explanation for such crack behavior.
    In FIG. 3 (middle picture, MoCu 18at%) it can be seen that the cracks in MoCu 18at% are largely parallel but no longer straight. In Figure 3 (right image, MoCu 52at%) an already tougher crack pattern can be clearly seen. Cracks with a tougher character usually run through the entire layer thickness, but not necessarily over the entire width of the sample, which means that conductive connections remain in the material. The slope of the R / R o curve is lower in this case (the curve rises less quickly), as can be seen in FIG. 2.
    Even from a small Cu content in the Mo-based layer, the critical elongation c k is significantly increased and the occurrence of cracks is reduced. If the Cu content is increased further, the crack behavior changes from brittle towards tough. Cu as an additive to Mo is therefore particularly characterized by the fact that even low additions lead to a considerable increase in the toughness of the Mo-based layer and that Cu is comparatively cheap as a material.
    In FIG. 11, X-ray diffractograms of two MoCu layers with a Cu content of 18% and 34% are shown. Diffractograms of a pure Mo or Cu layer are also included as a reference. All layers were deposited by means of DC sputtering on a silicon wafer at room temperature (without substrate heating) and have a thickness of 500 nm. The crystal structure was recorded with a Bruker-AXS D8 diffractometer, which is equipped with a Cu-Ka X-ray source, in grazing incidence mode with an angle of incidence of 2 °. The positions of the x-ray reflections of cubic, body-centered (krz) molybdenum (room group Im3m) are shown as vertical dotted lines, and the vertical positions of the reflex positions of cubic, face-centered (car) copper (room group Fm-3m) are used as references; the data were taken from the database of the ICDD (International Center for Diffraction Data). As can be seen in FIG. 11, the two high-copper-containing systems MoCu-18 at.% And MoCu-34 at% do not have a separate Cu phase, since the corresponding reflections are missing in the diffractogram. It can therefore be assumed that the Cu is present in the molybdenum in the form of a mixed crystal, i.e. H. that the copper atoms occupy molybdenum lattice sites. The copper atoms thus distort the Mo lattice. The two Mo (110) and Mo (200) reflections also point to the distorted Mo lattice, which are shifted towards higher diffraction angles (2 theta) compared to the undistorted reference, since the Cu atom (atomic radius 128 pm) is smaller than one Mo atom (140 pm).
    In addition, the sheet resistance p (pOhmcm) of the various Mo or MoCu thin layers is given in Table 2 in the last column (500 nm layer thickness on an insulating glass substrate). For the measurement, the specific surface resistance R s (ohm / sheet) was measured using the four-point method and multiplied by the layer thickness. The sheet resistance of the MoCu layers increases up to a Cu content of 34at.%, And then decreases again with increasing Cu content. All MoCu layers have a sheet resistance of less than 150 pOhmcm.
    In the case of multilayer layers made of MoCu / Cu or MoCu / ΑΙ, the sheet resistance along a long conductor track is determined primarily by the more conductive material Cu or Al. A two-layer layer of 50 nm MoCu34-at.% And 300 nm Cu above (deposited on a non-conductive glass substrate) has a sheet resistance of 2.0 pOhmcm. A two-layer layer of 50 nm MoCu34-at.% And 300 nm Al above it has a sheet resistance of 3.1 pOhmcm.
    It is assumed that the mechanical properties of the layers examined
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    Patent office can be further optimized. It is therefore likely that the microstructure and the residual stress state of the deposited Mo-based layers can be further optimized through targeted heat treatments. The growth of the layers can also be influenced in a targeted manner by specifically setting the deposition conditions, and it is very likely that a further increase in toughness can be achieved.
    EXAMPLE 2:
    In the course of several test series, different metallic Mo-based layers were deposited on polyimide substrates. Layers with different chemical compositions were manufactured.
    The compositions of the metallic Mo-based layers are summarized in Table 3.
    Table 3: Chemical composition of the sputtered MoAg layers
    Mo [at%] Ag [at%] Layer 1 82 18 Layer 2 69 31 Layer 3 56 44 Layer 4 48 52
    Pure Mo in the form of a molybdenum layer with a thickness of 50 nm was used as the reference material for the molybdenum-based alloys.
    All layers were deposited on a 50 μm thick film made of polyimide (PI, for example “Kapton®”) at room temperature. The process parameters were kept constant in order to rule out the influence of different process conditions on the results as much as possible. The layer thickness was kept constant at 50 nm in order to avoid the influence of geometric effects on the results.
    The substrate surface was completely coated, there were no smaller structures by z. B. etching process.
    The critical strains c k determined by means of a tensile test, as described in Example 1, are listed in Table 4.
    Table 4: Critical strain c k of the examined Mo and MoAg layers, as well as the difference to the reference sample made of pure Mo. Furthermore, the sheet resistance of a 500 nm thick layer on a non-conductive borosilicate glass (Corning Eagle XG) is given.
    material critical elongation c k Ac k Sheet resistance p (pOhmcm) Mo 1.10% reference 22 Mon 18at% 1.16% 0.06 96 Mon 31at% 1.52% 0.42 138 Mon 44at% 2.31% 1.21 111 MoAg 52at.% 3.81% 2.71 101
    After the tensile test described above, the tested layers were examined in a light microscope and scanning electron microscope. The shape of the cracks and the mean distance between the cracks that occurred in the layers were assessed.
    In a layer based on a brittle material, such as pure Mo, the crack usually occurs when the sample fails under tensile stress, which is typical for brittle material behavior. This is due to a network of straight, parallel 10/31
    AT15 574U2 2018-03-15 Austrian
    Patent Office found cracks that form approximately at right angles to the direction of loading. Such a crack pattern can be seen, for example, in FIGS. 5 (Mo, left). These straight cracks usually run from side to side across the entire width of the sample and through the entire thickness of the layer. Such cracks are also called Through Thickness Cracks (TTC). TTCs considerably reduce the electrical conductivity of the layer, since in the worst case there is no longer a continuous conductive connection in the layer. As can be seen in the curves measured on the reference materials, the electrical resistance increases very strongly with increasing elongation.
    This can be seen in FIG. 4, which shows the increase in electrical resistance compared to the output resistance (R / R o ) compared to the applied strain ε.
    The critical strains in Table 4 from the failure criterion R / R o = 1.1 show that from a critical Ag content in the layer of greater than 18 at.%, The toughness of the layer is noticeably increased, as shown in FIG Figure 4 and Table 4 can be seen. It is believed that this increase in toughness is caused by an easier dislocation movement in the material. This subsequently leads to an increase in the critical elongation and to a reduced occurrence of TTCs. Ag as an additive to Mo is therefore particularly characterized in that higher additions lead to a very high increase in the toughness of the Mo-based layer.
    As an example, Figure 4 shows the resistance curves R / R o of the various MoAg samples. The appearance of the cracks still corresponds to the TTCs as can be seen from FIG. 5 (top right), but the critical elongation e k has already been significantly increased.
    Another effect that can be observed in addition to increasing the critical elongation e k is that the appearance of the cracks changes from a brittle to a tough material behavior. Cracks that are typical for tough material behavior can be recognized by the fact that the cracks are no longer straight, but rather have a zigzag course. Redirecting the cracks at the crack tips is a possible explanation for such crack behavior.
    In Figure 5 (picture MoAg 44at%) it can be seen that the cracks in MoAg 44at% are largely parallel but no longer straight. In Figure 5 (MoAg 52at%) an already tougher crack pattern can be clearly seen. Cracks with a tougher character usually run through the entire layer thickness, but not necessarily over the entire width of the sample, which means that conductive connections remain in the material. The slope of the R / R o curve is lower in this case (the curve rises less quickly), as can be seen in FIG. 4.
    From a critical Ag content in the Mo-based layer of 18% by weight, the critical elongation e k is significantly increased and the occurrence of cracks is reduced. If the Ag content is further increased, the crack behavior changes from brittle towards tough.
    The X-ray diffractograms of the deposited MoAg layers are shown in FIG. The layer deposition and analysis of the crystal structure was carried out analogously to the MoCu system (FIG. 11). The diffractograms of a pure Mo or Ag layer are also included as a reference. The positions of the x-ray reflections of cubic body-centered (krz) molybdenum (space group lm-3m) are shown as vertical dotted lines in FIG ; the data were taken from the database of the ICDD (International Center for Diffraction Data). As can be seen in FIG. 12, the MoAg systems do not have a separate Ag phase up to a silver content of 44at.%, Since the corresponding reflections are missing in the diffractogram. It can therefore be assumed that the Ag is forcibly dissolved in the molybdenum, in the form of a mixed crystal, i. that is, the silver atoms occupy molybdenum lattice sites. The silver atoms thus distort the Mo lattice. The two Mo (110) and Mo (200) reflections also indicate the distorted Mo grating, which, compared to the undistorted reference, indicate lower diffraction angles (2 theta)
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    Patent office are postponed because the Ag atom (atomic radius 165 pm) is larger than a Mo atom (140 pm). Only in the MoAg-52at.% Layer is there a hint of (220) silver reflex, which indicates that a separate silver phase in the krz-molybdenum matrix is beginning to separate out.
    In the MoCu or MoAg thin layers, the copper or silver (element X) is therefore present in the krz-molybdenum lattice. The crystal structure of pure gold (Au) is the same as that of Cu and Ag (space group Fm-3m). All three elements are in the same subgroup (11) of the periodic table of the chemical elements and show a similar chemical and physical behavior in many respects. It can therefore be assumed that sputtered MoAu thin films with Au contents below 40at.% Are in the form of a mixed crystal in which the gold atoms in the krz-Mo matrix are forcibly dissolved.
    Furthermore, the sheet resistance p (pOhmcm) of the various Mo or MoAg thin layers is given in Table 4 in the last column (500 nm layer thickness on an insulating glass substrate). For the measurement, the specific surface resistance R s (ohm / sheet) was measured using the four-point method and multiplied by the layer thickness. The sheet resistance of the MoAg layers increases up to an Ag content of 31at.%, And then decreases again with increasing Ag content. All MoAg layers have a sheet resistance of less than 150 pOhmcm.
    In the case of multilayer layers made of MoAg / Cu or MoAg / AI, the sheet resistance along a long conductor track is determined primarily by the more conductive material Cu or Al. A two-layer layer of 50 nm MoAg 31at.% And 300 nm Cu above (deposited on a non-conductive glass substrate) has a sheet resistance of 2.0 pOhmcm. A two-layer layer of 50 nm MoAg 31at.% And 300 nm Al above it has a sheet resistance of 3.1 pOhmcm.
    One or more metallic layer (s), as specified in claim 2 and possibly in one of the further developments, can be part of a thin-film transistor (TFT). The layer structure of such an electrical thin-film component is shown in cross section in FIG. The TFT consists of a semiconductor layer 150, a gate electrode 120, a source electrode 170a, and a drain electrode 170b, at least one of these three metallically conductive electrode layers consisting of the metallic layer according to the invention. The gate electrode 120 is separated from the semiconductor layer 150 by an electrically insulating layer (gate insulator, gate dielectric) 140. The source electrode 170a is separated from the drain electrode 170b by an electrically insulating passivation layer 180. Furthermore, this passivation layer 180 also separates the source / drain electrodes 170a / 170b from the pixel electrode layer 190 (apart from the contact hole described below).
    The general layer structure of a bottom-gate TFT, as shown in FIG. 6 according to one embodiment, is described below. The TFT layer structure is arranged on a flexible substrate 100. First, a buffer layer 110 can be arranged on the flexible substrate 100, which covers the entire substrate 100, in order to compensate for any unevenness on the upper side of the flexible substrate 100 or to prevent undesired impurities from penetrating into the semiconductor layer 150, for example by diffusion or permeation , The buffer layer can e.g. consist of a single-layer or multi-layer layer containing silicon oxide or silicon nitride.
    [00111] The gate electrode 120 is arranged over the buffer layer 110. By applying an electrical voltage, an electrically conductive channel can be created in the semiconductor layer 150 due to an electrical field effect, which electrically connects the source electrode 170a to the drain electrode 170b. The gate electrode 120 can consist of the metallic layer according to the invention, or of a metallization according to the state of the art made of a single or multi-layer layer which contains at least aluminum (Al), copper (Cu), silver (Ag), gold (Au ), Platinum (Pt), molybdenum (Mo), tungsten (W), titanium (Ti), chrome, (Cr), niobium (Nb), tantalum (Ta).
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    Patent office An electrically insulating layer (gate dielectric) 140 is arranged above the gate electrode 120. This electrically insulating layer 140 can, for example, be a layer made of silicon oxide, silicon nitride, aluminum oxide, or an electrically insulating organic material such as e.g. Include benzocyclobutene (BCB) or an acrylic-containing material.
    The semiconductor layer 150 is adjacent to the electrically insulating layer (gate dielectric) 140 and z. B. include amorphous silicon (a-Si), poly-silicon, a metal oxide semiconductor such as indium gallium zinc oxide (IGZO), or an organic semiconductor. In the case of a semiconductor layer 150a which contains a-Si, an n + -doped semiconductor layer 150b can also be arranged above this layer, for example containing phosphorus-doped a-Si. In the case of a semiconductor layer 150a which contains a metal oxide semiconductor such as IGZO, the doped semiconductor layer 150b is generally omitted.
    [00114] The source and drain electrode layers 170a and 170b are arranged above the semiconductor layer 150. These layers can consist of the metallic layer according to the invention, or of a metallization corresponding to the state of the art, consisting of a single or multi-layer layer which contains at least aluminum (Al), copper (Cu), silver (Ag), gold (Au), platinum (Pt ), Molybdenum (Mo), tungsten (W), titanium (Ti), chromium, (Cr), niobium (Nb), tantalum (Ta).
    [00115] The passivation layer 180 is arranged above the semiconductor layer 150 and the source / drain electrode layers 170a / 170b. This electrically insulating passivation layer 180 can, for example, be a layer of silicon oxide, silicon nitride, aluminum oxide, or an electrically insulating organic material such as e.g. Include benzocyclobutene (BCB) or an acrylic-containing material.
    The passivation layer 180 is interrupted by a contact hole which electrically connects the adjacent pixel electrode layer 190 to the drain electrode 170b. The pixel electrode layer 190 is electrically conductive and can be designed as an optically transparent layer or as an optically reflecting layer and can be embodied in one or more layers. If the pixel electrode layer 190 is embodied as an optically transparent layer, it can include, for example, indium-tin oxide (ITO), indium-zinc oxide (IZO), zinc oxide (ZnO), or aluminum-zinc oxide (AZO). If the pixel electrode layer 190 is formed as an optically reflective layer, it can include a reflective layer made of Al, Ag, Mg, Pt, Pd, Au, Nd, Ni, Ir, and a layer including indium tin oxide (ITO). , Indium zinc oxide (IZO), zinc oxide (ZnO), or aluminum zinc oxide (AZO).
    [00117] The TFT described here can be part of a flexible TFT-LCD display or OLED display.
    One or more metallic layer (s), as specified in claim 2 and possibly in one of the further developments, can be part of a system-on-panel (SOP) system in which a TFT active matrix display is arranged together with peripheral electronic control units on a substrate. An SOP is shown in Figure 7. The display unit 1 can consist, for example, of a liquid crystal display (LCD), an organic light-emitting diode (OLED), an inorganic light-emitting diode (LED), or an electrophoretic display (“E-Ink®”; “e-paper”). The display unit 1 represents the actual visible part of the display on which the image content is shown. Around this area, several driver and control circuits are arranged on the substrate, which are usually hidden behind an opaque part of the housing, which is not visible to the user. In principle, one or more of the electronic circuits described below can be arranged on the SOP, although this list is not exhaustive and, depending on the display unit used, further circuits may be necessary for activation.
    To control the display unit 1, a horizontal data driver circuit (column driver) 2a / b can be arranged on the substrate, which via the data lines (not shown) with the source / drain electrodes 170a / b of the TFT (not shown) ) connected is. A gate 13/31 can be arranged on the substrate to control the gate electrodes 120
    AT15 574U2 2018-03-15 Austrian
    Patent Office
    Driver structure (line driver) 3 are located, which is connected via the gate lines (not shown) to the gate electrodes 120 of the TFTs (not shown).
    Furthermore, a DC-DC converter circuit 4 can be arranged in the peripheral area, which converts a lower input voltage into a higher output voltage; to control a TFT-LCD display could e.g. A voltage of +3.3 to +5.0 V is present at the input, which is converted into a higher output voltage in the range -40 to + 40V ("charge pump"), which is required to control the liquid crystal.
    Furthermore, an electrical circuit 5 can be arranged on the SOP, which provides a reference voltage (Vcom, e.g. + 5V for an LCD display) for the display unit 1.
    [00122] Furthermore, a timing controller circuit (TCon) 6, a digital-to-analog converter circuit 7, a discharge stage 8, and a Vcom buffer circuit 9 could be arranged on the substrate.
    The SOP is connected via a contacting area 10 to the other components of the display control electronics or a graphics card.
    The peripheral circuits 2 to 9 are interconnected, with the display unit 1 and the contacting area (“pad contacts”) 10 with the metallic layer according to the invention (not shown).
    The contacting of the display unit 1 is shown as an example in FIG. The row driver 3 is connected to the display unit 1 via electrical conductor tracks 20, the column driver 2b is connected to the display unit 1 via electrical conductor tracks 21. One or both conductor tracks 20 or 21 can consist of the metallic layer according to the invention, as specified in claim 2 and possibly in one of the further developments.
    9 shows the contacting of a thin film transistor (TFT) with the gate and data lines. The gate conductor track 20 has an extension in the region of the TFT, which forms the gate electrode 120 of the TFT. The data conductor track 21 has an extension in the area of the TFT, which forms the source electrode 170a of the TFT, and an area interrupted by the source electrode, which forms the drain electrode 170b of the TFT, and which is connected to the pixel electrode 190 is. One or both conductor tracks 20 or 21 or the TFT electrodes 120, 170a / b can consist of the metallic layer according to the invention, as specified in claim 2 and possibly in one of the further developments.
    Furthermore, one or more metallic layer (s), as specified in claim 2 and possibly in one of the further developments, are part of a low temperature poly-silicone (LTPS) thin-film transistor (TFT), the layer structure of which is in cross section is shown by way of example in FIG. In comparison to the TFT structure from FIG. 6, this is a top-gate TFT, ie the gate electrode 240 is arranged above the semiconductor layer 220 and not below it. LTPS TFTs are preferably designed as top-gate TFTs. Compared to amorphous silicon (0.5 - 1.5 cm 2 / Vs), the LTPS semiconductor has a significantly higher charge carrier mobility (50 - 200 cm 2 / Vs). This means that such a TFT can also be used to control current-driven displays such as OLEDs or micro LEDs.
    In the following, the layer structure for a top-gate LTPS TFT is described as an example. The LTPS-TFT is arranged on a flexible substrate 200. First, a buffer layer 210 can be arranged on the flexible substrate 200, which covers the entire substrate 200, in order to compensate for any unevenness on the upper side of the flexible substrate 200 or the penetration of undesired impurities into the semiconductor layer 220 or into doped semiconductor regions 221 (source electrode ) and 222 (drain electrode), for example by diffusion or permeation. The buffer layer 210 may e.g. consist of a single-layer or multi-layer layer, the silicon oxide, silicon nitride, or
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    Includes silicon oxynitride. Depending on the nature of the substrate, the buffer layer can also be dispensed with.
    The semiconductor layer 220, which may consist of undoped, polycrystalline silicon, is arranged on the buffer layer 210. Adjacent to this layer 220 (also called “channel area”) is a source electrode 221 on one side and a drain electrode 222 on the other side, which can each consist of doped polysilicon. The doping can be done, for example, by ion implantation; By using boron (B) or B 2 H 6 , for example, p-doping can be achieved. Depending on the design of the TFT, the type of doping (p or n) or the type of dopant can vary.
    A gate insulator layer 230 is arranged over that of the semiconductor layers 220, 221 and 222. This gate insulator layer 230 can e.g. consist of silicon nitride or silicon oxide. The gate electrode 240 is arranged on the gate insulator layer 230 in such a way that it has at least a certain area overlap (in the vertical direction) with the channel area (semiconductor layer 220). The gate electrode 240 can consist of the metallic layer according to the invention, or of a metallization according to the state of the art consisting of a single or multi-layer layer which contains at least aluminum (Al), copper (Cu), silver (Ag), gold (Au ), Platinum (Pt), molybdenum (Mo), tungsten (W), titanium (Ti), chrome, (Cr), niobium (Nb), tantalum (Ta). The gate electrode 240 is connected via gate lines (not shown) to the control electronics (not shown), among others. the line drivers.
    Over the gate electrode 240 or the gate insulator layer 230, an insulating layer 250 is applied, which may consist of a similar material as the gate insulator layer 230, for. B. silicon nitride or silicon oxide. The insulating layer 250 and the gate insulator layer 230 are provided with through holes which make the source and drain electrodes 221/222 of the semiconductor layer (electrically) accessible.
    A drive or contacting source electrode layer 260 and a drive or contacting drain electrode layer 270 are arranged above the insulating layer 250 and through the above-described through holes with the source / drain electrodes 221/222 of the semiconductor connected. The drive or contacting source / drain electrode layers 260/270 can consist of the metallic layer according to the invention or of a metallization according to the prior art made of a single or multi-layer layer which contains at least aluminum (Al), copper (Cu), Silver (Ag), Gold (Au), Platinum (Pt), Molybdenum (Mo), Tungsten (W), Titanium (Ti), Chrome, (Cr), Niobium (Nb), Tantalum (Ta). The control or contacting source electrode layer 260 is connected via the data lines (signal lines; not shown) to the control electronics, u. a. connected to the column drivers (not shown).
    The thin film transistor is formed from the semiconductor layer 220, the gate electrode 240, and the drive or contacting source / drain electrode layers 260/270. However, the configuration of the TFT is not limited to the exemplary embodiment described above, but can also have numerous other configurations which can be easily implemented by an expert.
    A planarization layer 280 can also be arranged above the TFT structure, in particular if further light-emitting layers, e.g. OLED layers are arranged (not shown). The planarization layer 280 can e.g. a polyacrylate resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, an unsaturated polyester resin, a polyphenylene ether resin, a polyphenylene sulfide resin, or benzocyclobutene (BCB). The planarization layer 280 is provided with a through hole which makes a region of the drive or contacting drain electrode layer 270 accessible.
    A pixel electrode layer 290 is shown as an example in FIG. 10, which is attached above the planarization layer 280 and which is electrically conductively connected to the drive or contacting drain electrode layer 270 via the through hole. in the
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    In the case of an LTPS-OLED display, the pixel electrode layer 290 forms the first electrode (usually the anode in the case of an upward-emitting structure) of a light-emitting structure. If the pixel electrode layer 290 is embodied as an optically transparent layer, it can include, for example, indium-tin oxide (ITO), indium-zinc oxide (IZO), zinc oxide (ZnO), or aluminum-zinc oxide (AZO).
    If the pixel electrode layer 290 is formed as an optically reflective layer, it can contain a reflective layer made of Al, Ag, Mg, Pt, Pd, Au, Nd, Ni, Ir, as well as a layer containing indium tin oxide ( ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or aluminum zinc oxide (AZO).
    [00137] It is assumed that the mechanical properties of the layers examined can be further optimized. It is therefore likely that the microstructure and the residual stress state of the deposited Mo-based layers can be further optimized through targeted heat treatments. The growth of the layers can also be influenced in a targeted manner by specifically setting the deposition conditions, and it is very likely that a further increase in toughness can be achieved.
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    LIST OF REFERENCE NUMBERS:
    R
    ro
    Ro ε
    ck
    Lconst
    P
    2a / b
    20 21 100 110 120 140 150 170a 170b 180 190 200 210 220 221 222 230 240 250 260 270 280 290 electrical resistance of the layers electrical resistance at the start of the measurement of specific surface resistance maximum expansion critical expansion fixed clamping length within which no expansion takes place
    sheet resistance
    display unit
    Data driver circuit (column driver)
    Gate driver structure (line driver)
    DC-DC converter circuit electrical circuit
    Timing controller circuit (TCon)
    Digital to analog converter circuit
    discharge stage
    buffer circuit
    Contacting area ("pad contacts") electrical conductor tracks electrical conductor tracks flexible substrate
    buffer layer
    Gate electrode insulating layer (gate insulator, gate dielectric)
    Semiconductor layer
    Source electrode
    Drain electrode electrically insulating passivation layer
    Pixel electrode layer flexible substrate
    buffer layer
    Semiconductor layer doped semiconductor regions (source electrode) doped semiconductor regions (drain electrode)
    Gate insulator layer
    Gate electrode insulating layer
    Driving or contacting source electrode layer Driving or contacting drain electrode layer Planarization layer
    Pixel electrode layer
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    权利要求:
    Claims (20)
    [1]
    Expectations
    1. Coated flexible component containing:
    - a flexible substrate (100, 200)
    - At least one layer structure arranged directly or via one or more intermediate layers on the substrate (100, 200), which has a metallic layer with a bisecting or electrically insulating layer immediately adjacent to the metallic layer on one side and the metallic layer on the other side Layer immediately adjacent semiconducting or electrically insulating layer, characterized in that the metallic layer is formed from:
    - a single layer of MoX, or
    a two-layer system made of MoX in combination with a Cu-based layer or made of MoX in combination with an Al-based layer, or
    - a three-layer system consisting of two MoX layers with an intermediate Cubas layer or of two MoX layers with an Al-based layer, X being one or more elements from the group of Cu, Ag, Au.
    [2]
    2. Component according to the preceding claim, wherein in at least one MoX layer X the
    Element is Cu and this MoCu layer contains more than 0.5 at% and less than 50 at% Cu.
    [3]
    3. Component according to claim 1 or 2, wherein in at least one MoX layer X the element is Ag and this MoAg layer contains more than 10 at% and less than 50 at% Ag.
    [4]
    4. Component according to at least one of claims 1 to 3, wherein in at least one MoX layer X the element is Au and this metallic MoAu layer contains more than 5 at% and less than 20 at% Au.
    [5]
    5. The component according to at least one of claims 1 to 4, wherein X dissolved in the Mo layer in
    Form of a mixed crystal is present.
    [6]
    6. Component according to at least one of claims 1 to 5, wherein the individual MoX layer has a sheet resistance p of less than 200 gOhmcm.
    [7]
    7. Component according to at least one of the preceding claims, wherein the flexible substrate (100, 200) is formed separately from the electrically insulating layers.
    [8]
    8. The component according to at least one of claims 1 to 6, wherein the flexible substrate (100,
    200) is formed by one of the semiconducting or electrically insulating layers directly adjacent to the metallic layer.
    [9]
    9. The component according to at least one of the preceding claims, wherein at least one of the semiconducting or electrically insulating layers immediately adjacent to the metallic layer is formed as layers (140, 150, 220, 250).
    [10]
    10. The component according to at least one of the preceding claims, wherein the thickness of the metallic layer is less than 1 gm, preferably less than 500 nm, preferably 5 to 100 nm.
    [11]
    11. The component according to at least one of the preceding claims, wherein the flexible substrate (100, 200) is transparent.
    [12]
    12. The component according to at least one of the preceding claims, wherein the metallic layer has an overall sheet resistance p less than 50 gOhmcm.
    [13]
    13. Component according to at least one of the preceding claims, wherein the flexible substrate (100, 200) comprises at least one material from the following group:
    - polymer
    - thin glass
    - metal foil
    - mineral material.
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    Patent Office
    [14]
    14. Component according to at least one of the preceding claims, wherein the metallic layer at 2% elastic elongation (ε) has a ratio of the electrical resistance (R) to the electrical resistance at the start of the measurement (R o ), (R / R o ) of less 1.2.
    [15]
    15. Component according to at least one of the preceding claims, wherein the coated flexible component (100, 200) has at least one conductor track structure and it is preferably provided that the metallic layer is part of the at least one conductor track structure.
    [16]
    16. The component according to at least one of the preceding claims, wherein the metallic layer is part of a TFT structure.
    [17]
    17. The component according to at least one of the preceding claims, wherein the metallic layer is part of an active matrix structure.
    [18]
    18. Component according to at least one of the preceding claims, wherein the coated flexible component is a component from the following group: flexible LCD display, flexible OLED display, flexible electrophoretic display (e-paper, E-Ink®), flexible solar cell, electrochromic flexible Foil, flexible thin-film battery.
    [19]
    19. A method for producing a coated flexible component according to one of claims 1 to 18, comprising at least the following steps:
    - Providing a flexible substrate (100, 200)
    - Coating the flexible substrate (100, 200) - directly or via one or more intermediate layers - by depositing at least one MoX layer, characterized in that the MoX layer contains more than 0.5 at% X, where X is one or more Elements from the group of Cu, Ag, Au.
    [20]
    20. The method according to the preceding claim, wherein the deposition of the at least one metallic layer is realized by means of a PVD method.
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    JP2019561901A| JP2020522728A|2017-05-11|2018-04-19|Flexible component with a layered structure having a metal layer|
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    KR1020197036521A| KR20200008575A|2017-05-11|2018-04-19|Flexible part comprising a layer structure with a metal ply|
    PCT/AT2018/000026| WO2018204944A1|2017-05-11|2018-04-19|Flexible component having a layered structure with a metallic ply|
    TW107114884A| TW201903177A|2017-05-11|2018-05-02|a flexible component comprising a layer structure having a metallic interlayer|
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